The present invention relates to the fabrication of semiconductor integrated circuits, and in particular, to cleaning compositions and methods for cleaning surfaces during fabrication.
In the fabrication of semiconductor integrated circuits (ICs), active device regions are formed in semiconductor substrates, isolated from adjacent devices with an isolating material. Electrical paths connect such active devices, using thin-film structures, such as metal lines/patterned metal layers. Such structures make contact with active devices through openings, or contact holes, in the isolating material. One primary concern in forming such interconnects is the maintenance of a low level of resistivity throughout an IC in order to ensure devices perform properly. As ICs are scaled down in size, so are the devices which make up the ICs. Increases in resistance are associated with increasing circuit density and adversely affect device performance, slowing them down and increasing power consumption. Thus, ways to decrease the overall resistance of ICs are crucial to continued successful device performance.
In many applications, the metal lines/patterned metal layers are formed on a different level than the active devices, separated by an insulating layer, such as, for example, silicon dioxide or borophosphosilicate glass (BPSG). Furthermore, there may be more than one level of metal lines/patterned metal layers, connected by conductive interconnects formed in vias defined in an insulating layer between adjacent metal lines/patterned metal layers. Commonly used metal lines/patterned metal layers include aluminum, to which copper may be added to form an alloy. Interconnects are also formed between individual devices and the metal lines/patterned metal layers. A typical interconnect to an active device region is formed in a contact hole defined in an insulating layer over the active device region. The contact hole is filled with one or more metals, such as, for example, aluminum or tungsten.
In lowering resistivity of an IC, it is important to remove all foreign residue from interfaces in the IC. As multiple layers are formed in ICs, individual layers may need to be cleaned before the next layer is formed or before surface modification is done. Numerous preclean procedures exist for use prior to semiconductor surface modification in batch furnaces, including wet chemical cleans, hydrogen bakes, phosphoric acid, arid hydrofluoric acid (HF) vapor cleans. Many cleaning compositions undesirably contain strong, i.e., not dilute, organic solvents, which typically are disposed of using special hazardous waste disposal techniques.
Preclean procedures are important to both reduce native oxide and remove other contaminants, such as, for example, residual organic and metallic impurities. Residual photoresist and other organic materials used in processing steps, such as, for example, etches, are often hard to remove from surfaces during IC fabrication. In particular, such residual materials are hard to remove from metal surfaces and surfaces adjacent to metal layers due to the metallization of such organic residue on the surfaces, particularly as a result of intermixing of materials during etch steps. Thus, metal layers and vias have been hard to effectively clean in the past after completion of patterning etches and via etches through insulating layers thereon. Further, conventional cleaning compositions used are typically hazardous and require special handling and disposal procedures.
Therefore, for the reasons as described above, there is a need for effective cleaning compositions and methods of cleaning surfaces during fabrication of ICs. For example, a composition and method for cleaning metal surfaces during fabrication is needed to remove metallized organic residue from surfaces during IC fabrication in order to lower the resistivity of resulting ICs. Further, it is desirable that the cleaning compositions utilized can be disposed of safely and easily.
A cleaning method in a semiconductor fabrication process according to the present invention includes providing a dilute composition consisting essentially of phosphoric acid and acetic acid and exposing a surface to the dilute composition. In one embodiment of the method, the dilute composition includes phosphoric acid at a concentration of about 5% or less by volume and acetic acid at a concentration of about 30% or less by volume. More preferably, in one embodiment of the dilute composition, the dilute composition includes phosphoric acid at a concentration of about 5% or less by volume and acetic acid at a concentration of about 10% or less by volume. In another embodiment, the dilute composition includes phosphoric acid at a concentration of about 5% or less by volume and acetic acid at a concentration in the range of about 20% by volume to about 30% by volume.
Another cleaning method according to the present invention includes providing a composition comprising phosphoric acid and acetic acid, wherein the composition includes phosphoric acid at a concentration of X%, wherein X is about 5% by volume or less, and acetic acid at a concentration of about (100xe2x88x92X%) by volume or less. A surface is then exposed to the composition. In one embodiment of the method, the composition is a dilute composition, wherein the dilute composition includes phosphoric acid at a concentration of about 5% by volume or less, acetic acid at a concentration of about 30% by volume or less, and deionized water. In another embodiment, the surface is of a conductive layer.
A method of fabricating an interconnect structure according to the present invention is also provided. The method includes patterning a conductive layer and cleaning the conductive layer using a composition comprising phosphoric acid and acetic acid. The composition includes phosphoric acid at a concentration of about X% or less by volume, where X is 5, and acetic acid at a concentration of about (100xe2x88x92X)% or less by volume. In one embodiment of the method, the composition is a dilute composition, and further, the dilute composition includes phosphoric acid at a concentration of about 5% or less by volume and acetic acid at a concentration of about 30% or less by volume. In another embodiment, the dilute composition includes phosphoric acid at a concentration of about 5% or less by volume and acetic acid at a concentration of about 10% or less by volume.
In another embodiment of the method, the conductive layer comprises aluminum. Further, the patterning may include patterning the aluminum layer using a chlorine-containing etchant and a photoresist which results in organic residue on at least a part of the conductive layer. The cleaning then removes the organic residue, e.g. a metallized organic residue.
In addition, a method of fabricating a multilevel interconnect structure is described. The method includes providing an insulating layer over a first metal layer. A via is defined in the insulating layer resulting in residue on an exposed portion of the first metal layer. The residue is removed using a dilute cleaning composition consisting essentially of phosphoric acid and acetic acid. The dilute cleaning composition includes phosphoric acid at a concentration of about 5% or less by volume and acetic acid at a concentration in the range of about 20% by volume to about 30% by volume.
Yet another method according to the present invention includes providing a structure including an aluminum containing conductive region and providing a dilute composition consisting essentially of phosphoric acid, acetic acid, and deionized water. The structure is then exposed to the dilute composition to clean at least the aluminum containing conductive region. Preferably, the dilute composition includes phosphoric acid at a concentration of about 5% or less by volume and the acetic acid at a concentration of about 30% or less by volume.
In various embodiments of the above methods, the surface is of a conductive layer. Preferably, when exposing the conductive layer to the composition, etching of the conductive layer occurs at a rate of less than about 200 xc3x85/minute. More preferably, such etching of the conductive layer occurs at a rate of less than about 50 xc3x85/minute. Further, preferably, etching of the conductive layer occurs such that less than about 500 xc3x85 of conductive material is removed from the conductive layer during an exposure period of less than 10 minutes; preferably, less than about 200 xc3x85 during an exposure period of less than 10 minutes; more preferably, less than about 50 xc3x85 during an exposure period of less than 10 minutes.
A cleaning composition for use in semiconductor integrated circuit fabrication according to the present invention consists essentially of a dilute aqueous solution of phosphoric acid and acetic acid. The phosphoric acid is of a concentration of about 5% by volume or less and the acetic acid is of a concentration of about 30% by volume or less. Preferably, in one embodiment, the phosphoric acid is of a concentration of about 5% or less by volume and the acetic acid of a concentration of about 10% or less by volume. In another embodiment, the phosphoric acid is of a concentration of about 5% or less by volume and the acetic acid is of a concentration in the range of about 20% by volume to about 30% by volume.
Another cleaning composition for use in semiconductor integrated circuit fabrication according to the present invention includes phosphoric acid and acetic acid. The composition includes phosphoric acid at a concentration of about X% by volume or less, where X is 5, and acetic acid at a concentration of about (100xe2x88x92X)% by volume or less. In one embodiment, the composition is a dilute composition, wherein the dilute composition includes phosphoric acid at a concentration of about 5% by volume or less, acetic acid at a concentration of about 30% by volume or less, and deionized water.